As the semiconductor technology heads towards miniaturizing the transistor size, the transistor noise increases dramatically, degrading the accuracy and the reliability of integrated circuits. Various techniques have thus been proposed for suppressing the transistor noise. Contrarily, several applications have found noise useful for data encryption, for perturbative learning in bio-inspired computations, for stochastic arithmetic, and for probabilistic modeling. The arithmetic architecture with noisy transistors has been also proposed. These applications normally require multichannel uncorrelated noise in hardware implementation. While conventional noise generators are based on cellular automata, the feasibility of using the transistor noise has also been exploited by using silicon nitrides to increase interface traps and miniaturizing transistors to have single-oxide traps. However, these methods simply enhance the noise to a usable extent without controlling the exact noise level.
FIG. 1 shows the layout of a typical FET and a corresponding cross-sectional view thereof. As shown in the upper part of FIG. 1, the layout includes a gate 16 above an active region 14, and a source contact 11 and a drain contact 13 at two opposite sides of the gate 16, respectively. Cut from the line A-A in the layout, the corresponding cross-sectional view of the FET is shown in the lower part of FIG. 1. In standard CMOS logic technology, a shallow trench isolation (STI) 12 is formed on a silicon substrate 10 to define the active region 14, and the gate 16 is deposited above the active region 14, so that the gate voltage VG applied to the gate 16 can modulate the channel 18 under the surface of the active region 14. The interface between the gate dielectric 20, which is sandwiched between the gate 16 and the channel 18, and the active region 14 has many dangling bonds that behave as traps, which will trap and de-trap carriers in the channel 18 and thereby induce low-frequency fluctuation. In the fabrication of FETs, it always employs special process, for example, the RCA clean applied to the surface of the active region 14, to minimize the dangling bonds in the interface and thus reduce the low-frequency noise induced by the interface. U.S. Pat. Publication Nos. 20070296025 and 20100057820 add a trap insulator in the gate dielectric 20 to provide more traps to enhance the low-frequency noise, while the level of the generated low-frequency noise can not be modulated by external voltages or currents. U.S. Pat. Publication No. 2009/0309646 enhances the fluctuation frequency of the low-frequency noise by changing the material of the channel 18, the material of the source and drain, or the shape of the liner covering the gate 16. However, these arts still can not adapt the amplitude or frequency of the low-frequency noise by external voltages or currents.
On the other hand, it is known that STI edge effect will induce noise in flash memories. It is pointed out by R. V. Wang, Y. H. Lee, Y. L. R. Lu, W. McMahon, S. Hu, and A. Ghetti, “Shallow trench isolation edge effect on random telegraph signal noise and implications for flash memory,” IEEE Trans. Electron Devices, vol. 56, no. 9, pp. 2107-2113, September 2009, that rounding STI corners may significantly decrease the number of the stress induced traps.
To date, additional masks or process modification are required to enhance the low-frequency noise of a FET, and thus the FET can not be fabricated with a standard CMOS logic process. Moreover, no prior arts have been found for a FET to adapt its low-frequency noise in amplitude.